Field of Invention
The present invention relates a manufacturing method of a MOS device, in particular to a manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device.
Description of Related Arts
After the feature size of semiconductor devices enters the 45 nm technology node and beyond, in order to reduce gate tunneling current, decrease the power consumption of the devices, thoroughly eliminate the problem of poor reliability caused by polysilicon depletion effect and boron penetration in a P-type metal-oxide-semiconductor field effect transistor (MPOSFET) and relieve a Fermi level pinning effect, it has become an inevitable choice to use high dielectric constant (k) oxide and metal gate materials to replace the traditional SiO2/polysilicon structures. However, according to the International Technology Roadmap for Semiconductor (ITRS), the CMOS technology will step into a 16 nm technology node in 2015-2020. The scaling-down of CMOS logical devices will be confronted with more challenges. In order to overcome these obstacles caused by size scaling-down, the most advanced process technologies need to be integrated into the product manufacturing process. According to the current development trend, application of new technologies which will be introduced into the 16 nm technology node involves the following several aspects: immersion lithography extended technology, mobility enhanced substrate technology, ultra-shallow junction (USJ) and other strain enhancement engineering methods, wherein increasingly extensive attention is paid to the mobility enhanced substrate technology. Due to extremely high carrier mobility and compatibility with semiconductor process, germanium (Ge) is considered as the most potential high-mobility semiconductor material. The band gap width of germanium is 0.66 eV, the electron mobility and the hole mobility are respectively 2.6 times and 4.2 times of that of Si, the mobility can also be further improved through the strain enhancement technology, and thus germanium is an ideal channel material for the next generation CMOS devices. However, the properties of the oxides of Ge are different from that of the oxides of Si, and GeO2 easily absorbs water molecule at normal temperature and becomes instable. Moreover, when temperature rises, GeO2 reacts with Ge to produce GeO, so that the high-k/Ge structure interface is caused to be instable under the MOS process. In addition, serious mutual diffusion easily occurs on the high-k/Ge interface, so that problems such as decreasing in performance of the dielectric layer and serious current leakage in the gate of the device are also caused.
In consideration of the challenges confronted by the high-k/Ge interface structure, graphene is considered as one of the most stable two-dimension materials and has ultrahigh flexibility and mechanical strength. According to the latest studies, graphene not only has ultrahigh carrier mobility, but also has a very good passivation effect. Through studies, it is found that metal materials can be favorably prevented from being oxidized by growing graphene on the surface of copper or copper-nickel alloy through the chemical vapor deposition method. By introducing graphene between Ni, Al, Au and the Si substrate, it can be used as the passivation layer under the condition of high temperature to favorably inhibit atom diffusion between different thin layers. In addition, according to studies, the conductor property of graphene can be transitioned to semiconductor and even insulator through H, O or F plasma treatment. Therefore, by introducing a plasma treated graphene barrier layer between the high-k gate dielectric material and the germanium substrate, it is promising to solve the problems of the production of instable GeOx and the mutual diffusion between Ge and the high-k oxide without influencing the property of channels. The research result will expand the application field of graphene materials and push the microelectronic technology to continuously develop according to Moore's law.